Some programmable integrated circuits (ICs), such as field programmable gate arrays (FPGAs) and system on chip (SOC) products from XILINX®, Inc., have a configurable, mesh-like structure for routing clock signals from clock sources to synchronous circuit elements (“clock loads”) of the circuit design. A clock source is a circuit that generates or provides a clock signal, such as a phase-locked loop (PLL), a high-speed serializer-deserializer (SERDES), or an input/output pin. Clock sources and clock loads of a circuit design are placed at locations on the programmable IC as part of the design implementation process.
At early stages in the design implementation flow, the clock loads are partitioned based on their placement. The clock load partitioning is driven by clocking architectural constraints of the programmable IC and is helpful in the allocation of routing resources during routing of the clock signals. Without suitable partitions of clock loads, a routing solution might be unattainable for the final placement.